Be A Part Of Billion Dollar Business – Chip Designing Made Easy
Introduction
The word of Chip designing means building an integrated Chip by integrating billions of transistors to achieve an application. An Application could be suiting a particular requirement like MicroprocessorRoutercell phoneetc. An Integrated circuit designed for a specific application is called as ASICApplication Specific Integrated Circuits.
Todays ASIC Chips is prettly complex packed with larger chunk of transistors targetted to a specific manufacturing process for fabricating the integrated circuits in a sub nanometer regime involving lots and lots of challenges like knowledge of various protocols architectures models formats standards knowledge about CMOS logic Digital Design concepts taming the EDA tool for the various design requirement’s like area timing power thermal noise routability lithography aware knowledge about Various variabilities like channel length Vt line width variations lens abrreations IR drop effectsinterdie intra dievariations effects and various noiseeffects like Package noiseEMI noisepower grid noisecrosstalk noise and ability to test and validate and know to model and characterize all these effects upfront in the designphasesteps to increase yield to increase profitability curve with short span of timeto market to minimize the risk and maximize the predictability and an modular approach to Success. Now let’s dwelve in to the Art of Chip Designing
Used lot of Technical Jargons nothing to worry about we will get in there soon…Be with me promise you understand the Concepts behind Chip Desiging.
Before Designing a Chip? Need to Brain Storm
1. What market the Chip is targetted for?
2. What are the Protocols involved in the Chip?
3. What is going to be our Processor/Bus Architecutes?
4. what is the power/IRdrop/timing/Area/Yield/ targets and how to budget it in the Chip?
5. What is the process in which the Chip going to be manufactured?
7. what are the various third party IP’s/Memory requirements?
8. what is our Design flow and EDA tools and methodology involved?
9. What is the estimated Chip Cost?
10. Above all the bottom line of any business model is money What will be our Profit model estimation of our ROIReturn of investment.
To know the Concepts of Chip DesigingFREE Access!!!
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Analogy of Chip Design Architecture Vs Building Architecture
Why an Analogy with Building ArchitectureIt is just to understand the concepts of Chip desiging in a better way as we are very familiar with Building Architecture then it will be easy for us to map Chip Design architecture.
VLSIVery large scale Integration flow was evolved similar to the flow involved in Building Construction.Now let us dwelve in to the constuction flow to better understand the VLSI Chip design flow development.
When ever we start to construct a building we will have an architecture how the building should look like the exterior looks and all similar to that we will be designing an architecture in the chipdesign based on the requirement of the product what the product is addressed for and whom to serve what needs the so called specification will having the modules.
Now lets go in to the implementation part of both the Building amp; Chip.
We at first come with the floorplan of the building similarly we come with the floorplan of the Chip Based on the connectivity/accessibility/vaasthu we place our rooms similarly we have the constraints to place the blocks. Like we build the building with bricks for Chip Design we have libraries which are like predesigned bricks for a specific functionality.
Now let us try to understand the powerstructure or electrical connectivity in our Building. Initially we have an Electrical plan for our building where we have a requirement that all our electrical gadgets needs to get power. Similar to that we have a Chip power requirement The required power is supplied through the powerpads over a ring like topology to have a uniform distribution across all corners of the chip and the supply has to reach all the standardcellsbricks for ChipDesigning.this is called as powergrid topology in the ChipDesign now the requirement is how well we design our Powergrid to reduce the IRdrop so that our standardcells get proper power requirement.
I would not make justice if I dont discuss about clock and clocktree in the ChipDesign flow. We have synchronous way of designing and asynchronous way of designingdifficult to verify. Majority of chips follow Synchronous way of coding for which Static Timing Analysis is possible. For the relevancy of the flops the clock to those flops should reach at the same time from the crystal with in some skew targets with in the chip.In order to make this happen a step called as clocktree is performed after powergrid is created.
Let us try to visualize the concept behind Place amp; Route in Chip Design. We need to undergo lot of modelling concepts to understand the process of ChipDesigning. To have a better understanding of this concept of place and route let us assume a society where people who are speaking different languages are living and let us visualize that people talking of the same languages are living in a community then the communication is much easier similar way in the chipdesigning the standardcells who are having design relationships are placed closer in the Placement flow this concept is called as regioning. Now with in the regioning of the groups of the standardcells the cells which are really sharing data has to placed closeby so that there timing is achieved and well optimized.This step is called placement Connectivity across the standardcells is called as routing the challenge is having optimized or reduced wirelengths.
Now let us try to try to understand the concept behind signal integrity in the ChipDesign often called us SI Effect. As our process is shrinking day by day and our siliconrealestate is costly we try to accommodate more and more standardcells in the limited area so the cells are placed in very close proximity so the switching of one can have an impact over the others behaviour which can make the path to be faster or slower this issue is called as signalintegrity. So similar way in our construction in order to maintain the integrity with in the houseneighbour freezone within the limited zone of modurality we try to create fences across buildings similarly we can think of a concept called as Shielding the high frequency signal net with the powernets running across. We perform spacing across the buildings similar way we can perform spacing across the nets which are in close proximities.
In order to validate the silicon from the manufacturability issues the concept in the Chip Desigining is Design for TestDFT. One of the DFT techniques is scanchain. To understand the concept of the scanchain we can visualize that we have a frontdoor entry and a backdoor exit and a person passes from the frontdoor and exits from the backdoor exit of the building that we are sure that there is no blocking within the rooms in the building to make that person stuck similar to this analogy the flipflops are connected together creating a scanchain and testinput values are passed from the scanchain input of the chip and expected data is visualized in the scanchain output of the chip then the assumption is the chip is free from manufacturability issues like stuckat faultsstuckat one or stuck at zeros.
To know the Concepts of Chip DesigingFREE Access!!!
www.vlsichipdesign.com
About the writer: Chip Design Veteran
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